1. Field of the Invention
This invention relates generally to the detection of faults in a digital computer system. More specifically, it relates to the detection of a "stuck" fault in a signal representing the value of the branch condition during the execution of a conditional branch instruction.
2. Background Information
The ability to make decisions by conditional branching is an essential requirement for any computer system which performs useful work. Conditional branch instructions may be used to construct such high-level programming constructs as loops and if-then-else statements. Because loops and if-then-else programming constructs are so common, it is essential that the conditional branch instructions which implement them execute as efficiently as possible.
The decision to branch or not to branch may be based on one or more events. In most computer systems these events are referred to as conditions and are represented as bits in a condition code (CC) register. Examples of conditions include positive, negative or zero numbers, overflow, underflow, and carry from the last arithmetic operation, and many others. When a CC register is used, the condition is tested by examining the relevant bits in the CC register, which were previously set by arithmetic/logical unit (ALU) operations. An advantage of this approach is that the condition bits are sometimes set without any negative effect on the time for executing instructions. A disadvantage is that condition codes constrain the ordering of instructions since they pass information from one instruction to an immediately following branch instruction. Nevertheless, this method is used by most prior art systems.
Some systems use the "compare and branch" approach. Under this approach, the compare is actually part of the branch instruction. Thus, two instructions (compare, branch) are now combined into one instruction, thereby potentially saving time. However, the set of conditions is often limited under this method and the actual implementation may be more complex and require just as much processing time as the two separate instructions.
A third approach is the use of a condition register to hold the value of the condition to be tested. This approach has the advantage being very simple. The disadvantage is that it uses up a register solely to store the condition. One way to eliminate this disadvantage is to store the condition in a register or designator on a device that is external to the processor. This approach will only be feasible if access to the external designator is obtained in an efficient and error-free manner.
There are two ways to quickly communicate the value of the external designator back to the processor, both of them involving signal lines. Since the external condition is a boolean value, two signal lines could be used to represent the possible values (i.e., one line for True, one line for False). Under this approach, both lines are initially set to a logic low state. During the processing of an external conditional branch instruction, the processor senses the state of each line. If the True line was set to a logic high, the processor knows that the branch condition is True. If the False line was set to a logic high, the processor knows that the branch condition is False. The True and False lines are then set to logic low after branch instruction processing is complete. It would be an error condition for both lines to be logic low or both lines to be logic high during an access. This would happen, for example, if the True line was stuck logic low and the branch condition was really true. The False line would then be logic low. Since both lines are logic low, the processor detects the stuck fault. A similar situation occurs when one of the lines is stuck logic high.
The problem with this approach is that it requires two lines to communicate a boolean value. It would be more efficient to be able to communicate the branch condition by using only one signal line. Thus, if the processor senses a logic high on the line, it would interpret the branch condition as True. If the processor senses a logic low on the line, it would interpret the branch condition as False. This approach saves pin connections because it uses only one line. However, if the line gets stuck at either a logic high or logic low state due to a hardware failure, the branch condition will always be represented as the same state, regardless of the actual value of the branch condition. When this occurs, the processor will at times branch or not branch instruction control erroneously and the stuck fault will escape detection. What is needed is an efficient method of communication over one signal line that detects this stuck fault condition before the error propagates throughout the system.